Tutorial Speakers

Monday, November 9

TUTORIAL I 9:00-10:30
Sparsity-Aware Machine Learning Processor

Prof. Yongpan Liu

Prof. Yongpan Liu
Tsinghua Univ.

Abstract

Sparsity is widely existed in modern neural networks and how to support such sparsity in hardware is an important direction to enhance energy efficiency of machine learning chips. This tutorial will first begin with an introduction of various pruning algorithm techniques to achieve sparse neural network (i.e. unstructured and structured sparse networks). Furthermore, we review different up-to-date architectures and chips to make efficient inference and training of sparse neural network, covering both spatial domain as well as time domain sparsity. Finally, we discuss challenges and future directions to support sparsity in computing-in-memory artificial intelligent chips.

Biography

Yongpan Liu received the B.S., M.S., and Ph.D. degrees from the Electronic Engineering Department, Tsinghua University, Beijing, China, in 1999, 2002, and 2007, respectively. He was a Visiting Scholar with Pennsylvania State University, and the City University of Hong Kong. He is currently an Associate Professor with the Department of Electronic Engineering, Tsinghua University. Prof. Liu is a Program Committee Member for DAC, DATE, ASP-DAC, ISLPED, ICCD, and A-SSCC. He has received under 40 Young Innovators Award DAC 2017, Micro Top Pick 2016, the Best Paper Award from ASPDAC2017, HPCA 2015, and Design Contest Awards of ISLPED in 2012 and 2013. He served as the General Chair for AWSSS 2016 and IWCR 2018 and the Technical Program Chair for NVMSA 2019. He is an Associate Editor of the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II, and the IET Cyber-Physical Systems.

TUTORIAL II 10:50-12:20
Ultra-Low-Power DTC-Based Fractional-N Digital PLL Techniques

Prof. Kenichi Okada

Prof. Kenichi Okada
Tokyo Inst. of Tech.

Abstract

In this tutorial, some design techniques for fractional-N digital PLL will be introduced to improve both jitter and power consumption especially for low-power applications. A highly-linear and low-power DTC and TDC will be presented as well as system-level optimization. An isolated constant-slope DTC realizes 10bit 0.1mW operation with 26MHz reference clock, and sub-ps INL is achieved. The DTC-based AD-PLL achieves FoM of -246dB with 0.98mW power consumption and -56dBc worst-case fractional spur. For further power saving, duty-cycled FLL, sub-sampling/sampling switching, charge-recycling DTC, and transformer-based DCO for impedance peaking will be also explained, which achieves 0.265mw power consumption with FoM of -237dB at 2.4GHz. Finally, a DPLL-based ADC and a BLE transceiver using DPLL will be introduced.

Biography

Kenichi Okada received the B.E., M.E., and Ph.D. degrees in Communications and Computer Engineering from Kyoto University in 1998, 2000, and 2003, respectively. From 2000 to 2003, he was a Research Fellow of the Japan Society for the Promotion of Science in Kyoto University. In 2003, he joined Tokyo Institute of Technology where he is now a Professor of Electrical and Electronic Engineering. He was a recipient or co-recipient of the Ericsson Young Scientist Award in 2004, the A-SSCC Outstanding Design Award in 2006 and 2011, the ASP-DAC Special Feature Award in 2011 and Best Design Award in 2014 and 2015, the RFIC Symposium Best Student Paper Award in 2019, the Kenjiro Takayanagi Achievement Award in 2020, the IEEE CICC Best Paper Award in 2020. He is/was a member of the technical program committees of IEEE International Solid-State Circuits Conference (ISSCC), VLSI Circuits Symposium, European Solid-State Circuits Conference (ESSCIRC), Radio Frequency Integrated Circuits Symposium (RFIC), and he also is/was Guest Editors and an Associate Editor of IEEE Journal of Solid-State Circuits (JSSC), an Associate Editor of IEEE Transactions on Microwave Theory and Techniques (T-MTT), a Distinguished Lecturer of the IEEE Solid-State Circuits Society (SSCS).

TUTORIAL III 13:40-15:10
Introduction to Silicon Photonics Systems and Their Modeling

Prof. Jaeha Kim

Prof. Jaeha Kim
Seoul National Univ.

Abstract

Silicon photonics systems integrate photonic components such as optical waveguides, coupler, resonator, etc. along with electronic components on the same silicon chip to realize high-bandwidth, high-density, and low-power communication. This tutorial provides an overview on common photonic devices such as microring modulator, Mach-Zehnder modulator, electro-absorption modulator, etc, and demonstrates how to model various wavelength-division multiplexing (WDM) systems tightly interacting with analog or digital electronic components and simulate them efficiently in SystemVerilog.

Biography

Jaeha Kim received the B.S. degree in electrical engineering from Seoul National University in 1997, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1999 and 2003, respectively. From 2001 to 2003, he was with True Circuits, Inc., USA, as a Circuit Designer. He was with Rambus Inc. as a Principal Engineer from 2006 to 2009, Stanford University as an Acting Assistant Professor from 2009 to 2010. In 2010, he joined Seoul National University, where he is currently an Associate Professor. In 2015, he founded Scientific Analog, Inc., an EDA company involved in analog/mixed-signal verification. Prof. Kim served on the Technical Program Committees of the International Solid-State Circuits Conference (ISSCC), the Custom Integrated Circuits Conference (CICC), the International Conference on Computer-Aided Design, and the Asian Solid-State Circuit Conference (A-SSCC). He was cited as a Top 100 Technology Leader of Korea in 2020 by the National Academy of Engineering of Korea. He was a recipient of the Takuo Sugano Award for Outstanding Far-East Paper at the 2005 International Solid State Circuits Conference (ISSCC) and the Low Power Design Contest Award at the 2001 International Symposium on Low Power Electronics and Design.

TUTORIAL IV 15:30-17:00
Integrated Security Interface Against Cyber-Physical Attacks

Prof. Noriyuki Miura

Prof. Noriyuki Miura
Osaka University

Abstract

The continuous growth in computing technology emerges various advanced information services today. The information managed in such services is becoming increasingly critical and hence valuable for malicious attackers. In order to steal, destroy, or manipulate such information in a cyber domain, the attackers exploits security holes in a physical domain computing entity i.e. IC hardware. This so-called cyber-physical attacks are currently one of the most serious security threats in realizing future advanced information society where the information security is the-root-of-trust of all the critical services such as autonomous driving, drone guard, and robot nursing. This tutorial lecture will cover several key countermeasures namely integrated security interface against the cyber-physical attacks, including 1) power/EM side-channel, 2) EM/laser fault-injection, 3) chip-package-board hardware counterfeiting, and 4) sensor spoofing attacks. Future perspectives on the information security in the next-generation society will also be covered.

Biography

Noriyuki Miura received the B.S., M.S., and Ph.D. degrees in electrical engineering all from Keio University, Yokohama, Japan. From 2005 to 2008, he was a JSPS Research Fellow and since 2007 an Assistant Professor with Keio University, where he developed wireless interconnect technology for 3D integration. In 2012, he moved to Kobe University, Kobe, Japan, and became a Professor at Osaka University, Suita, Japan in 2020. Also, he was concurrently appointed as a JST PRESTO researcher, and now working on hardware security/safety and next-generation heterogeneous computing systems. Prof. Miura is currently serving as a Technical Program Committee (TPC) Member for A-SSCC and Symposium on VLSI Circuits. He served as the TPC Vice Chair of 2015 A-SSCC. He was a recipient of the Top ISSCC Paper Contributors 2004-2013, the IACR CHES Best Paper Award in 2014.